1. Field of Use
The present invention relates to arithmetic processing units and more particularly to arithmetic units which perform floating point operations.
2. Prior Art
In general, an arithmetic processing unit has been designed to afford more flexibility in the types of operations it is required to perform. For example, certain arithmetic processing units are required to process instructions specifying operations involving different operand forms. More specifically, in the case of floating point arithmetic, in certain types of instructions such as those specifying multiply and divide operations, the operands include a short mantissa value (e.g., 56 bit value). For other types of instructions, such as those specifying addition and subtract operations, the operands can include a long mantissa value (i.e., 64 bit value) for certain phases in their execution.
To accommodate the long and short operand requirements of such instructions, data processing units have included separate exponent and mantissa sections wherein the mantissa section is expanded to include a sufficient number of stages for handling the largest size mantissa value required to be processed.
The above arrangement has been found to add considerably to the amount of circuits within the arithmetic processing unit, resulting in increased space and cost.
Accordingly, it is an object of the present invention to provide an arithmetic unit which can handle different types of floating point operands with a minimum amount of additional circuits.
It is a further object of the present invention to provide an arithmetic unit which can process mantissa and exponent values without any degradation in performance.